1. Field of the Invention
The present invention relates to a semiconductor memory and a method for fabricating the same, and more specifically to a structure of a semiconductor memory such as a large-storage-capacity NOR type mask ROM, having buried digit lines, and a method for fabricating the same.
2. Description of Related Art
Now, a prior art will be described with reference to FIGS. 3 and 4. FIG. 3 is a plan view for illustrating a general cell layout in the NOR type mask ROM having buried digit lines. A plurality of buried digit lines 8 and active regions 6 are alternately located. A plurality of word lines 13 extend orthogonally to the buried digit lines 8. A region surrounded by a dotted line in FIG. 3 corresponds to a unitary cell. In FIG. 3, xe2x80x9cLxe2x80x9d indicates a channel length, and xe2x80x9cWxe2x80x9d indicates a channel width.
Next, a method in accordance with the prior art for fabricating the NOR type mask ROM having buried digit lines will be described with reference to FIGS. 4A to 4D, which are diagrammatic sectional views taken along the line Axe2x80x94A in FIG. 3 for illustrating the prior art method.
As shown in FIG. 4A, an oxide film 4 is formed on a P-type silicon substrate 1, and a photoresist film 5 is formed on the oxide film 4, and then patterned to have an opening at a region which is positioned between each pair of adjacent active regions 6 and where a buried digit line is to be formed in future. Then, as shown in FIG. 4B, N-type impurity, for example, arsenic, is implanted into the substrate 1 using the patterned photoresist film 5 as a mask. As a result, buried digit lines 8 are formed. After the photoresist film 5 and the oxide film 4 are removed, oxidation is carried out so that a gate oxide film 2 is formed on the surface of the substrate 1 as shown in FIG. 4C. Further, a polysilicon film 3 and a tungsten silicide film 11 are formed on the whole surface as shown in FIG. 4D, and then, are selectively removed so that the word line 13 constituted of a polycide gate electrode 12 formed of the tungsten silicide film 11 and the polysilicon film 3, is formed on the active region 6.
Incidentally, an example of the NOR type mask ROM is disclosed by Japanese Patent Application Pre-examination Publication No. JP-A-05-003303 (an English abstract of JP-A-05-003303 is available and the content of the English abstract is incorporated by reference in its entirety into this application).
In the above mentioned NOR type mask ROM, a layer resistance of the buried digit line is desired to be maintained even if the cell size is reduced, from the viewpoint of a demand in a circuit for ensuring a high speed operation margin. On the other hand, a margin of the channel length in a cell transistor (Lmin) should be ensured. For this purpose, it is desirable to reduce the dose of the N-type impurity in order to suppress a lateral diffusion. However, this results in an increased layer resistance of the buried digit line. Namely, the maintaining of the layer resistance of the buried digit line and the ensuring of the channel length margin (Lmin) of the cell transistor are a tradeoff relation against each other. In the prior art, therefore, it is difficult to reduce the cell size while simultaneously realizing both of the maintaining of the layer resistance of the buried digit line and the ensuring of the channel length margin (Lmin) of the cell transistor.
Accordingly, it is an object of the present invention to provide a semiconductor memory having a buried digit line, which has overcome the above mentioned problem of the prior art, and a method for fabricating the same.
Another object of the present invention is to provide a semiconductor memory having buried digit lines, which can reduce the cell size while simultaneously realizing both of the maintaining of the layer resistance of the buried digit line and the ensuring of the channel length margin of the cell transistor, and a method for fabricating the same.
The above and other objects of the present invention are achieved in accordance with the present invention by a semiconductor memory comprising a semiconductor substrate having a principal surface, a gate electrode which is formed on a gate insulator film formed in an active region on the principal surface of the semiconductor substrate and which is formed of a semiconductor layer and a conducting layer, grooves formed in self alignment with the gate electrode and to penetrate the inside of the semiconductor substrate, a buried digit line formed of a diffused layer which is formed within each of the grooves and which is of a conductivity type opposite to that of the semiconductor substrate, a first insulating film covering a surface of each of the grooves and at least a portion of a side surface of the gate electrode, a second insulating film filled up in the grooves and having a high reflow property, and a word line formed on the principal surface of the semiconductor substrate to extend orthogonally to the grooves, and constituting the gate electrode on the active region and functioning as an interconnection layer on the grooves.
According to another aspect of the present invention, there is provided a method for fabricating a semiconductor memory, comprising the steps of:
forming a semiconductor layer on a gate insulator film formed on a principal surface of a semiconductor substrate;
forming grooves to penetrate the inside of the semiconductor substrate in buried digit line formation regions which locate an active region between each pair of adjacent buried digit line formation regions;
introducing impurity of a conductivity type opposite to that of the semiconductor substrate, into at least a surface of the grooves in the semiconductor substrate;
depositing a first insulating film on the semiconductor substrate;
depositing a second insulating film having a high reflow property, to fill up the grooves having the surface covered with the first insulating film, and to planarize a surface of the semiconductor substrate;
removing the first insulating film and the second insulating film to allow the first insulating film and the second insulating film to remain only within the grooves;
forming a conducting layer on the semiconductor substrate; and
selectively partially removing the conducting layer and the semiconductor layer to form a word line extending on the principal surface of the semiconductor substrate orthogonally to the grooves, and constituting the gate electrode on the active region and functioning as an interconnection layer on the grooves.
With the above mentioned arrangement, even if the cell size is reduced, it is possible at least to maintain the layer resistance of the buried digit line.
In addition, if the grooves are formed to have a V-shape in a cross-section, even if the cell area is reduced, it is possible to simultaneously realize at least the maintaining and preferably the reducing of the layer resistance of the buried digit line, and the ensuring of the gate length margin (Lmin) of the cell transistor.
The grooves can be formed by performing an etching using a patterned photoresist film formed on the semiconductor layer as a mask, or alternatively by patterning an insulating film formed on the semiconductor layer and performing an etching using the patterned insulating film as a mask.
Preferably, the first insulating film covering a surface of each of the grooves and at least the portion of the side surface of the gate electrode, has an etching rate smaller than that of the second insulating film having a high reflow property and filling up the grooves.
In addition, the step of introducing the impurity of the conductivity type opposite to that of the semiconductor substrate, into at least the surface of the grooves in the semiconductor substrate, can be carried out by a slant rotating ion implantation.
Alternatively, the grooves are formed by performing an etching using a patterned photoresist film formed on the semiconductor layer as a mask, and in the step of introducing the impurity of the conductivity type opposite to that of the semiconductor substrate, into at least the surface of the grooves in the semiconductor substrate, the impurity is introduced into the semiconductor layer which was not doped the impurity to have the conductivity type opposite to that of the semiconductor substrate.
Furthermore, the semiconductor layer is formed of a polysilicon film or an amorphous silicon film. The semiconductor layer can be doped with impurity to have the conductivity type opposite to that of the semiconductor substrate when the semiconductor layer is formed, or alternatively, in a later step, the semiconductor layer can be doped with impurity to have the conductivity type opposite to that of the semiconductor substrate.
In addition, the conducting layer can be formed of a refractory metal film such as a tungsten silicide film, or alternatively can be formed of a polysilicon film or an amorphous silicon film.
The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.